Monthly Newsletter #3: Photons and Fault Lines
Welcome to this month's edition of what I've been thinking about in the technology space. Rather than recap market movements, a few ideas that may seem underweighted in the current conversation.
When Light Needs a Steady Hand
The process of manufacturing photonic integrated chips looks a lot like the semiconductor industry did thirty years ago. While the legacy transceiver market is mature, the move toward co-packaged optics (CPO) is a new frontier where there's no universal recipe for success. Every vendor has developed its own secret sauce for growing lasers and aligning fibers. Some processes feel almost artisanal, with technicians coaxing photons through waveguides the way a watchmaker assembles a movement. This fragmentation creates both opportunity and headaches as hyperscalers push to bring CPO into production at scale.
Two bottlenecks stand out. First, indium phosphide, the exotic material that makes high-performance lasers possible, has a geopolitical problem. Upstream refinement of III-V compound semiconductor materials remains heavily concentrated in China, which means any laser production outside Chinese borders carries supply chain risk that tariffs can amplify overnight. Second, coupling light from a tiny laser into an optical fiber demands sub-micron precision; shift by just one micron and you lose half your signal. Unlike transistors, which tolerate a bit of slop, photons are unforgiving. Heat makes things worse by subtly bending light paths and throwing off coupling. For CPO, where optics sit right next to hot silicon, thermal management and alignment must coexist in an unforgiving environment.
Shift Left
As chip complexity rises and advanced packaging becomes standard, the economics of testing are changing. A single faulty component discovered after packaging can force you to scrap an entire module. In heterogeneous designs where multiple die are integrated into one package, one failed component ruins everything around it. The industry response is to shift testing earlier in the production process, ideally to the wafer level before components are assembled.
This is the "shift left" strategy. Wafer-level probe testing verifies electrical functionality while chips are still on the wafer. Wafer-level burn-in subjects chips to high temperatures and voltages to weed out early-life failures before they reach expensive downstream stages. As we move toward 3D stacking, this extends to testing through-silicon vias (TSVs) before the stack is sealed. The goal is to identify known good die before they enter advanced packaging flows.
The broader point is that back-end test is at an inflection point. Disaggregated architectures require more die-level validation before assembly and more complex verification afterward. The more valuable the final package, the more the industry will spend to validate each component before integration. The companies that capture this complexity stand to benefit from a structural tailwind that extends well beyond the current cycle.
Where do you see as the most underweighted topics in tech for 2026? As always, I'd welcome your thoughts on any of this.
Until next month,
Jess Xu